AOS场效应管的功率放大解析寿命/AOZ1057AIL的资料下载地址,不一样的共享(下部)
2018-04-18 11:59:53
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对称放大电路所用元件要检测其静态特性。功率放大电路如图2所示。

The components of symmetrical amplification circuit must be tested for its static characteristics. The power amplifier circuit is shown in Figure 2.

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场效应管放大电路图大全(五款场效应管放大电路原理图详解)

The field effect transistor amplifying circuit diagram Daquan (five FET amplifying circuit schematic diagram detailed explanation).


以Tm1和Tm3为例,其检测参数主要是IDDS,即当VGS=0时的漏极电流。在VGS=0时,测出IDDS,其值相近为宜。同样地,Tm2和Tm4也要与Tm1或Tm3静态值相差无几,或相近。只有这4个场效应管静态值大致相同,才有可能做出优质的放大器来。成批生产的放大器价格很高,正是这些电路中使用的元件匹配困难,造成制造成本高,制约了该技术的推广应用。

Taking Tm1 and Tm3 as an example, the detection parameter is mainly IDDS, namely the drain current when VGS=0. At VGS=0, IDDS is measured, and its value is close. Similarly, Tm2 and Tm4 are almost the same as those of Tm1 or Tm3. Only if the static values of the 4 FET are approximately the same, it is possible to make high-quality amplifiers. The cost of mass produced amplifiers is very high, because the matching of components used in these circuits is difficult, resulting in high manufacturing cost, which restricts the popularization and application of the technology.

场效应管放大电路图(五)

Field effect tube enlargement circuit diagram (five)

对应三极管的共射、共集及共基放大电路,场效应管放大电路也有共源、共漏和共栅三种基本组态。下面以JFET组成的共源极放大电路为例,介绍场效应管放大电路的工作原理。

There are three basic configurations of common source, common drain and common gate, which are common emitter, common collector and common base amplifying circuit corresponding to triode. Next, take the common source amplifier consisting of JFET as an example, introduce the working principle of FET amplifying circuit.


1.自偏压电路

1. self bias circuit

自偏压电路如图3-10所示。在图中,场效应管栅极通过栅极电阻RG接地,源极通过源极电阻RS接地。这种偏置方式利用JFET(或耗尽型MOS管)在栅源电压uGS=0时,漏极电流iD≠0的特点,以漏极电流在源极电阻RS上的直流压降,给栅源之间提供反向偏置电压。也就是说,在静态时,源极电位uS=iDRS,由于栅极电流为0,RG上没有压降,栅极电位uG=0,所以栅源之间的偏置电压为

The self bias circuit is shown in Figure 3-10. In the figure, the gate of the field-effect transistor is grounded through the gate resistance RG, and the source electrode is grounded through the source resistance RS. This bias mode uses the JFET (or depletion type MOS tube) in the gate source voltage uGS=0, and the drain current iD 0 is characterized by the DC voltage drop of the drain current on the source resistance RS, providing the reverse bias voltage between the gate sources. That is to say, in the static state, the source potential uS=iDRS, because the gate current is 0, there is no pressure drop on the RG, the gate potential is uG=0, so the bias voltage between the gate sources is the same.

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uGS=uG-uS=-iDRS

UGS=uG-uS=-iDRS


要说明的是,自偏压方式不能用于由增强型MOS管组成的放大电路。因为增强型MOS管

It should be explained that the self bias way can not be used for amplifying circuit composed of enhanced MOS tube. Because of the enhanced MOS tube


只有当uGS达到UT时才有iD产生。

Only iD is produced when uGS reaches UT.


场效应管放大电路图大全(五款场效应管放大电路原理图详解)

The field effect transistor amplifying circuit diagram Daquan (five FET amplifying circuit schematic diagram detailed explanation).


对于图3-10电路的静态工作点,可以利用式(3-1)和式(3-3)求联立方程,即

For the static working point of Fig. 3-10, we can use the formula (3-1) and sum (3-3) to find simultaneous equations.


ID=IDSS(1-UGS/UP)2(3-4)

ID=IDSS (1-UGS/UP) 2 (3-4)

UGS=-IDRS(3-5)

UGS=-IDRS (3-5)


求得ID和UGS之后,则有

After getting ID and UGS, there are


UDS=VDD-ID(RD+RS)(3-6)

UDS=VDD-ID (RD+RS) (3-6)


例3-1电路如图3-10所示,已知IDSS=0.5mA,UP=-1V,试确定电路的静态工作点。

Example 3-1 circuit is shown in Figure 3-10. Known IDSS=0.5mA, UP=-1V, try to determine the static working point of the circuit.

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解:根据上面分析得到的公式有

Solution: the formula based on the above analysis


ID=0.5(1+UGS)2

ID=0.5 (1+UGS) 2


UGS=-2ID

UGS=-2ID


将UGS表达式代入ID表达式中,得

The UGS expression is replaced in the ID expression.


ID=0.5(1-2ID)2

ID=0.5 (1-2ID) 2


解方程得

Solution equation


ID=(0.75±0.56)mA

ID= (0.75 + 0.56) mA


而IDSS=0.5mA,ID不应大于IDSS,所以

And IDSS=0.5mA, ID should not be larger than IDSS, so


IDQ=0.19mA

IDQ=0.19mA


UGSQ=0.38V

UGSQ=0.38V


UDSQ=11.9

UDSQ=11.9

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2.分压式自偏压电路

2. partial pressure self bias voltage circuit

虽然自偏压电路比较简单,但是当静态工作点确定后,uGS和iD就确定了,因而RS选择的范围很小。分压式自偏压电路是在图3-10电路的基础上加接分压电阻后组成的,如图3-11所示。漏极电源VDD经分压电阻RG1和RG2分压后,通过RG3供给栅极电压,uG=RG2VDD/(RG1+RG2);同时漏极电流在源极电阻RS上也产生压降,uS=iDRS。因此,静态时加在JFET上的栅源电压为

Although the self bias circuit is relatively simple, when the static working point is determined, uGS and iD are determined, so the range of RS selection is very small. The divider self bias circuit is made up of voltage divider on the basis of figure 3-10 circuit, as shown in Figure 3-11. The drain source VDD is fed by the voltage divider RG1 and RG2 to supply the gate voltage by RG3, uG=RG2VDD/ (RG1+RG2); and the drain current also produces pressure drop on the source resistance RS, and uS=iDRS. Therefore, the gate source voltage added to the JFET at static time is the same.


uGS=uG-u=VDDRG2/(RG1+RG2)-iDRS(3-7)

UGS=uG-u=VDDRG2/ (RG1+RG2) -iDRS (3-7)


同样可根据式(3-1)和(3-7)求联立方程,即

Similarly, simultaneous equations can be obtained according to formula (3-1) and (3-7).


ID=IDSS(1-UGS/UP)2

ID=IDSS (1-UGS/UP) 2


UGS=VDDRG2/(RG1+RG2)-IDRS

UGS=VDDRG2/ (RG1+RG2) -IDRS


从而求出ID和UGS,并求出

Thus, ID and UGS are obtained and obtained.


UDS=VDD-ID(RD+RS)

UDS=VDD-ID (RD+RS)


得出电路的静态工作点。

The static working point of the circuit is obtained.

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3、场效应管放大电路的动态分析

3. Dynamic analysis of field effect transistor amplifying circuit

图3-10自偏压电路可以用图3-12的交流等效电路来表示,图中RL为放大电路外加的负载电阻。从图中不难求出电压放大倍数Au、Ri和Ro三个性能参数。

Fig. 3-10 self bias circuit can be represented by the AC equivalent circuit of figure 3-12, in which RL is a load resistor added to the amplifying circuit. It is not difficult to figure out three performance parameters of voltage amplification Au, Ri and Ro from the diagram.


场效应管放大电路图大全(五款场效应管放大电路原理图详解)

The field effect transistor amplifying circuit diagram Daquan (five FET amplifying circuit schematic diagram detailed explanation).


1.电压放大倍数Au

1. voltage magnification multiple Au


由图3-12可得出

From figure 3-12


Au=uo/ui=(-idR′L)/ugs=-(gmugsR′L)/ugs

Au=uo/ui= (-idR 'L) /ugs=- (gmugsR' L) /ugs


That is


Au=-gmR′L(3-8)

Au=-gmR 'L (3-8)


其中,R′L=RD∥RL。

The R 'L=RD' RL.

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式(3-8)表明,JFET共源放大电路的电压放大倍数Au与跨导gm成正比,且输出电压与输入电压反相。

The formula (3-8) shows that the voltage amplification factor Au of JFET common source amplifying circuit is directly proportional to the transconductance GM, and the output voltage is inverting with the input voltage.


2.输入电阻Ri和输出电阻Ro

2. input resistance Ri and output resistance Ro


由图3-12可得

Obtained from figure 3-12


Ri≈RG(3-9)

Ri = RG (3-9)


Ro≈RD(3-10)

Ro = RD (3-10)


可见,共源放大电路的输入电阻Ri主要由偏置电阻RG决定,而输出电阻Ro则由漏极电阻RD决定。

It can be seen that the input resistance Ri of the common source amplifying circuit is mainly determined by the bias resistance RG, while the output resistance Ro is determined by the drain resistance RD.


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